[Solved] Balancing the short trace requirement with the thermal ones

Lorenzo Marcantonio Asks: Balancing the short trace requirement with the thermal ones
I’m designing a substantial (200W) buck converter with the LT3840 controller (but the question is not really part specific). As usual with these parts the datasheet says:

  • Minimize the hot loop. (See Figure 9 [the power current loop])
  • Use short wide traces for the MOSFET gate drivers (TG and BG), as well as, gate drive supply and return (INTVCC and BOOST, BGRTN and SW) [the gate drive loop].

They also give a reference design which is actually quite interesting:


Reference layout

Looking for example at Q3-Q4 the gates are brought down with two vias and then routed to the controller in a big trace (it’s 1mm wide on a 70µm copper layer). Of course this is done to minimize trace inductance and resistance given the huge gates these MOSFET have and the potential switching frequency (it can go up to 1MHz).

However this power stage is almost too much compact… the thermal performance for the devices is usually given for a square inch of copper (usually single sided, if they use the JEDEC test coupon). In these condition they are working almost in their minimal footprint condition with some difficult to estimate improvement due to the four layers and thermal vias. Outer planes have something like 5×8mm for each MOSFET but the internal planes are almost solid copper and that helps a lot.

Now, my MOSFETs here have a RthJA of 50°C/W with a the square inch copper (they are 5×6); they don’t even quote the minimal footprint condition since it would be probably huge. I can’t afford a four layer and I don’t really think that a dual 70µm layer copper board in almost minimal footprint could reach that. If I really had to guess probably it would be about 75°C/W.

My idea was to spread the packages and add more radiant copper. I’m running at a quite low frequency (200kHz) to minimize switching losses (I’m trading inductance with ripple for the switching inductor, the resulting cost is the same) but, ideally, the last MOSFET would be at something like 70mm from the controller which doesn’t fit in my description of “short trace”, even when 1mm wide.

Is there some quantitative estimate for a limit? I was thinking of estimating the resulting gate trace impedance and compare it with the output driver one. If the resulting value is “well below” of the driver output resistance (say, less than 5-10%), the driver should work fine, right?

What could be the penalty except for a raise in switching losses?

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